The present invention relates to decoding and reconstruction of two channel MPEG-1 and/or multi-channel MPEG-2/AC-3 audio data. More specifically, the invention relates to decoding and reconstruction of audio data by performing a functional partitioning of the MPEG-1, MPEG-2 and AC-3 audio decoding algorithms, which partitioning allocates some of the decoding steps to be done in hardware and the remaining tasks to be done in firmware.
Various standards have been developed for the purpose of providing digitally encoded audio data that can be reconstructed to provide good quality audio playback. In the late 1980s, a digital audio/video reconstruction standard known as xe2x80x9cMPEGxe2x80x9d (for Motion Pictures Experts Group) was promulgated by the International Standards Organization (ISO). MPEG syntax provides an efficient way to represent audio and video sequences in the form of compact coded data. MPEG unambiguously defines the form of a compressed bit stream generated for digital audio/video data. Given the knowledge of the MPEG rules, one can thus design a decoder which reconstructs an audio/video sequence from the compressed bit stream.
MPEG was initiated in the early 1990s to define a syntax for higher quality audio playback for broadcast video. The MPEG-1 audio standard is described in a document entitled xe2x80x9cCoding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 MBit/sxe2x80x9d (Part 3 Audio) 3-11171 rev 1 (1995) (hereinafter xe2x80x9cthe MPEG-1 Documentxe2x80x9d). The MPEG-2 audio standard is described in a document entitled xe2x80x9cGeneric Coding of Moving Pictures and Associated Audio Informationxe2x80x9d ISO/IEC 13818-3 (1994) (hereinafter xe2x80x9cthe MPEG-2 Documentxe2x80x9d). Both standards documents are incorporated herein by reference for all purposes. Both documents are available from ISO/IEC Case Postale 56, CH-1211, Geneva 20, Switzerland.
A competing standard employing Dolby processing and known as xe2x80x9cAC-3xe2x80x9d has also been developed by the United States Advanced Television Systems Committee for digital encoding and decoding of audio data. This standard is described in the xe2x80x9cDigital Audio Compression (AC-3)xe2x80x9d draft ATSC STANDARDxe2x80x9d AC3STD68.DOC (1994) (hereinafter xe2x80x9cthe AC-3 Documentxe2x80x9d) which is available from Dolby Laboratories, Inc. located in San Francisco, Calif. and is incorporated herein by reference for all purposes.
The MPEG-2 audio decoding algorithm requires certain steps such as decoding of bit allocation, decoding of scale factors, variable length decoding of audio samples, requantization of samples, inverse discrete cosine transform matrixing, and windowing. The AC-3 audio decoding algorithm requires certain steps such as bit allocation, dequantization, decoupling, rematrixing, dynamic range compression, inverse fast fourier transform, and windowing and de-interleaving.
By way of example, audio decoder solutions like Six Channel Dolby Digital Surround Processor, Two Channel Dolby AC-3/MPEG-1 Audio Decoder, Programmable Dolby Digital AC-3/MPEG-2 Processor available from Zoran Corporation of Santa Clara, Calif. 6 Channel Audio Decoder IC, available from Thompson Multimedia of Hannover, Germany, and other products available from Compcore, USA and Aureal Inc, USA offer a purely software design or a purely hardware design. These designs, however, fail to offer the capability of decoding multi-channel audio and reconstruct a programmable number of output audio channels (specified by a customer) at a low system clock.
While CPU digital processing power has improved markedly in recent years, the purely software/firmware implementation alone cannot effectively decode the sheer volume of encoded audio data that must be rapidly decompressed and played back when decoding multi-channel MPEG-1, MPEG-2 or AC-3 audio data. CPUs like SPARC from Sun Microsystems, Inc. of Mountain View, Calif., MIPS from Silicon Graphics, Inc. of Mountain View, Calif., Pentium from Intel Corporation of Santa Clara, Calif., etc. cannot, in themselves, handle MPEG-2 audio decoding because they cannot meet the multi-channel audio frame decode time requirements at low system clock frequencies. Current designs described above decode AC-3 multi-channel audio data at a higher system clock and therefore require higher-power consumption. Furthermore, fully software/firmware-based audio decoders require large sized Code ROMs to achieve the decoding functionality, and are expensive.
A complete hardware implementation, which may employ a multiplier, for example, comes at the expense of large number of transistor device gates that consume a large chip area.
Thus, it would be desirable to find a way to perform a functional partitioning of the MPEG-1, MPEG-2 and AC-3 audio decoding algorithms such that the partitioning allocates some of the decoding steps to be done in hardware and the remaining tasks to be done in firmware.
The present invention provides a reusable hardware layout (xe2x80x9ccorexe2x80x9d) for performing some, but not all, MPEG and AC-3 audio decoding functions. The functional blocks comprising this xe2x80x9caudio corexe2x80x9d define a unique hardware architecture which can be used with additional hardware or software for performing those MPEG and AC-3 audio decoding functions not performed by the audio core.
Hereinafter, except where distinctions between the two versions of the MPEG standard exist, the terms xe2x80x9cMPEG-1xe2x80x9d and xe2x80x9cMPEG-2xe2x80x9d will be used interchangeably to reference those audio decoding algorithms promulgated in the original MPEG-1 Document as well as in the MPEG-2 Document, and any future versions of MPEG decoding. Likewise, the term xe2x80x9cAC-3xe2x80x9d is intended to refer to not only the current AC-3 standard, but any other versions of this standard that exist now or are developed in the future.
A chip designer may use the audio core of this invention to expedite the designing of an MPEG or AC-3 audio decoder. However, because the audio core of this invention performs only some of the MPEG and AC-3 decoding steps, the designer is free to design blocks, optimized for the designer""s purposes, to perform the remaining MPEG and/or AC-3 functions. The audio core of this invention is particularly useful for expeditiously designing xe2x80x9csystemxe2x80x9d chips containing multiple cores on a single chip. Such cores might include, for example, the audio core of this invention, a video core, and a CPU core.
A significant benefit of an audio core derives from its availability for repeated use in many different chips for different applications. In each such chip, the audio decoding functions specified by the audio core can be employed without redesign. Thus, the audio core may be used on a first integrated circuit having a first integrated circuit design and on a second integrated circuit having a second integrated circuit design, with the first and second integrated circuit designs having at least some features not in common. If a system chip is employed, the first integrated circuit design may include a first collection of cores, while the second integrated circuit may include a second collection of cores, etc.xe2x80x94even though the first and second collections of cores have at least one core not in common.
The audio core design itself is preferably stored on a machine readable media such as a magnetic or optical storage unit. The information content of the core preferably includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the audio core architecture. Ultimately, the audio core design is implemented as hardware on one or more chips. Thus, the audio core design exists as both an intangible description of hardware and as the actual hardware itself.
In a preferred embodiment, the audio decoder core design specifies that at least the following MPEG and AC-3 functions are performed by the hardware: sub-band synthesis (or xe2x80x9cmatrixingxe2x80x9d), downmixing and windowing. These functions are detailed in the MPEG Document and the AC-3 Document (as xe2x80x9cTransformation Equationsxe2x80x9d). In especially preferred embodiments, other MPEG-2 and AC-3 functions such as bit allocation decoding, scale factor decoding, variable length decoding, requantization, decoupling, rematrixing, and dynamic range compression are not performed by the audio core of this invention.
The present invention provides an audio core design having a data path for performing some functions (usually matrixing and windowing) of both MPEG audio decoding and AC-3 audio decoding. From a structural perspective, the data path should include at least one multiplier and at least one accumulator. Other architecturally distinct logical blocks of the audio core may be a control logic unit, an input RAM interface (for controlling an input RAM or controlling a samples input RAM and an intermediate values input RAM), an output RAM interface (for controlling an output RAM), a ROM, a ROM addressing logic unit, and a registers interface. The input RAM or samples input RAM and intermediate values input RAM and the output RAM are preferably located outside of the audio core.
Preferably, the control logic unit specifies in which state of multiple states the audio core currently resides, with each of the multiple states specifying one function or group of functions of either the MPEG or AC-3 decoding process. The control logic unit includes an MPEG state machine for generating MPEG state and cycle count information and an AC-3 state machine for generating AC-3 state and cycle count information. This information is employed by the RAM and ROM addressing logic to specify appropriate addresses for reading and writing data.
In one aspect the present invention provides a digital audio decoder having (i) an audio core which defines a hardware for matrixing and windowing during decoding of MPEG and AC-3 digital audio signals; (ii) an input RAM coupled to the audio core and configured to store discrete samples in preparation for matrixing and windowing and configured to store intermediate values that are calculated by the audio core during matrixing and written back to the input RAM.
The input RAM may be located outside of the audio core. An input RAM interface may control reading of samples from an input data partition of the input RAM and may control writing intermediate values generated during matrixing to one or more intermediate partitions of the input RAM. Furthermore, the input RAM interface may control reading intermediate values from the input RAM.
The input data partition for MPEG decoding algorithms may be provided in one location of the input RAM and the input data partition for AC-3 decoding algorithms may be provided in another location of the input RAM and the one or more intermediate partitions for MPEG decoding algorithms may be provided in one location of the input RAM and the one or more partitions for AC-3 decoding algorithms may be provided in another location of the input RAM.
The input data partition may be large enough to store at least 256 samples. At least one of the one or more intermediate partitions of the input RAM may store intermediate values for matrixing during decoding MPEG and AC-3 digital audio signals.
In one embodiment, the input RAM of the present invention includes a samples input RAM and an intermediate values input RAM, which is segregated from the samples input RAM. In this embodiment, the samples input RAM and the intermediate values input RAM may be located outside of the audio core. An input RAM interface may control reading of samples from the samples input RAM and may control writing intermediate values generated during matrixing to the intermediate values input RAM. The input RAM interface may also control reading intermediate values from the intermediate values input RAM. The samples input RAM may be large enough to store at least 256 samples. The intermediate values input RAM may include one or more partitions to store intermediate values for matrixing during decoding MPEG and AC-3 digital audio signals. The samples input RAM and intermediate values input RAM may be coupled to separate addressing logic.
In another aspect, the present invention provides a digital audio decoder having (i) means for decoding digital audio signals which defines a hardware for matrixing and windowing during decoding of MPEG and AC-3 digital audio signals; (ii) means for storing coupled to the means for decoding digital audio signals and configured to store discrete samples in preparation for matrixing and windowing and configured to store intermediate values that are calculated by the means for decoding digital audio signals during matrixing and written back to the means for storing. The means for decoding may be an audio core and the means for storing may be an input RAM.
In yet another aspect, the present invention provides a process of decoding MPEG and AC-3 digital audio signals, comprising: (i) providing a digital audio decoder including firmware and hardware that are configured to decode MPEG or AC-3 digital audio signals; (ii) receiving MPEG or AC-3 encoded digital audio signals; (iii) decoding at least partially the digital audio signals by the firmware using MPEG or AC-3 audio algorithms that precede matrixing and windowing; and (iv) performing matrixing, downmixing and windowing on MPEG or AC-3 digital audio signals by the hardware, wherein for a period of time the decoding the digital audio signals by the firmware and the performing matrixing and windowing by the hardware are carried out simultaneously.
The firmware may control the operation of a CPU and the hardware may define an audio core. The step of decoding using MPEG audio algorithms that precede matrixing and windowing may include the steps of decoding, bit allocation, decoding of scale factors and requantization. The step of decoding using AC-3 audio algorithms that precede matrixing and windowing may include the steps of providing a bit stream to an audio decoder, synchronizing the bit stream, unpacking BSI and side information, decoding exponents for current group of samples, bit allocation within the bit stream, unpacking, ungrouping, dequantizing and dithering mantissas, decoupling, rematrixing and dynamic range compression.
The above mentioned process of decoding MPEG and AC-3 digital audio signals may further include writing values produced as a result of the decoding by the firmware to a samples input RAM, after the step of decoding at least partially the digital audio signals by the firmware. The process may further still include: (i) performing downmixing and pulse code modulation by the hardware to produce an output; and (ii) writing the output produced by the hardware to an output RAM.
The step of decoding at least partially the digital audio signals by the firmware may include decoding at least partially audio data for a first channel using MPEG or AC-3 audio algorithms that precede matrixing and windowing to produce values for a first channel that are written to a samples input RAM; and the step of performing matrixing and windowing by the hardware may include performing matrixing and windowing on the values for the first channel to compute intermediate values that are written to an intermediate values input RAM.
In one embodiment of the present invention, the intermediate values input RAM is segregated from the samples input RAM. This embodiment may further include signaling the hardware to begin performing matrixing and windowing on the values for the first channel, when the firmware concludes writing the values for the first channel to the samples input RAM. Further still, this embodiment may include signaling the firmware to begin decoding at least partially audio data for a second channel using MPEG or AC-3 audio algorithms that precede matrixing and windowing, when the hardware consumes the values for the first channel in the input RAM to compute a first set of the intermediate values and completes writing the first set of the intermediate values to the intermediate values input RAM. The first set of intermediate values may be intermediate values produced after the hardware completes the pre-IFFT step of decoding AC-3 encoded data for the first channel. The first set of intermediate values may be intermediate values produced after the hardware completes the matrixing step of decoding MPEG encoded data for the first channel. This embodiment further still includes: (i) writing an output for the first channel to an output RAM after hardware completes decoding the audio data for the first channel; and (ii) waiting for the firmware to complete writing values for a second channel to the samples input RAM. The firmware may control the operation of a CPU and the hardware may define an audio core.
In yet another aspect, the present invention provides another process of decoding MPEG and AC-3 digital audio signals, comprising: (i) receiving input samples in a samples input RAM; (ii) matrixing the input samples in an audio core; (iii) writing intermediate values calculated during matrixing to an intermediate values input RAM; and (iv) windowing the intermediate values in the audio core.
The firmware and hardware partitioning of the decoding tasks in the present invention with a fully pipelined and (firmware and hardware) overlapped implementation helps in achieving multi-channel audio decoding and reconstruction within the available decode time operation with a low system clock.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.